1. Field of the Invention
The present invention relates to a method of establishing the correct display order of probe channels in a logic state analyzer, the analyzer having a plurality of probe channels, and a plurality of probe tips corresponding to the plurality of probe channels.
2. Description of the Prior Art
A typical electronics apparatus currently in use today includes a plurality of circuit boards, each of the circuit boards having a plurality of components connected thereto. Each component (or product under test) may further include a plurality of terminals, the terminals having signals applied thereto. A logic analyzer is used to measure and compare the signals present at each of the terminals of the product under test. The logic analyzer has a plurality of probe channels inherent therein. Each of these probe channels correspond to one of the terminals associated with the product under test. As the number of terminals increase, the number of channels in the logic analyzer also must increase. Some logic analyzers have 32, 64, 96, 104, or more channels inherent therein. When the operator is using this many channels in the logic analyzer, it is necessary for the operator to find an easy way to subdivide the channels into logical categories or groups. Typical groups may include 16 address lines, 8 data lines, and 5 control lines. Typical logic analyzers have one or more acquisition probes connected thereto, the probes including a plurality of probe tips. Each probe tip corresponds to one of the channels in the logic analyzer. The probe tips are connected to the individual terminals of the microprocessor or product under test. The signals present at each of the terminals are transmitted through the probe tips, through the acquisition probe, into the memory of the logic analyzer, and displayed on the logic analyzer display. The signals are represented by timing waveforms, and the individual timing waveforms are compared with one another on the display. However, as the number of terminals (and therefore the signals to be monitored) on the product under test increases, it is necessary for the operator to connect an increasingly higher number of probe tips to these terminals. It becomes increasingly more difficult for the operator to correctly connect all of the probe tips to their correct corresponding terminals of the product under test. In addition, due to the high number of terminals to be monitored, it was difficult to correctly analyze the voltage signals applied to these terminals using the timing waveform display mode.
Many times, the operator will connect the wrong probe tip to the wrong terminal of the product under test. This mistake is realized by watching the display of the logic analyzer. When he realizes this mistake, the operator must then exchange the probe tip connections such that the correct probe tip is connected to the correct terminal of the product under test. However, when this exchange is made, the operator may accidentally disconnect several of the other probe tips from their corresponding terminals. Assuming that the exchange is made correctly without disconnecting these other probe tips from their corresponding terminals, new data must then be acquired. This may present a problem, since, many times, this data is not available.
Other conventional logic analyzers include a vertical position control function for exchanging the vertical positions of the desired channel waveforms of the timing waveforms for comparing the desired channel timing waveforms with one another. This function is useful when using the timing display mode, that is, when displaying the acquired logic signals as timing waveforms. However, this function is not useful when using a state table mode display, that is, a display of the acquired logic signals as alphanumerics of a desired radix, such as binary, octal or hexadecimal. (See FIG. 3 for an example of a state table mode display).